Purdue Semiconductor Fabrication 101 Notes

I recently completed the free online course from Purdue Semiconductor Fabrication 101 and took some random notes.

finfet

Chenming Hu at UC Berkley

planar transistors harder to turn off when very small (expected sub 100nm but Intel used until 32nm)

1996 at 250nm, DARPA requests ideas for sub 25nm

1999 first finfet

2011 Intel switches to finfet at 22nm

https://en.wikipedia.org/wiki/Fin_field-effect_transistor

https://spectrum.ieee.org/how-the-father-of-finfets-helped-save-moores-law

https://spectrum.ieee.org/the-origins-of-intels-new-transistor-and-its-future

utb soi: ultrathin-body silicon-on-insulator

layer of insulator with thin layer of insulator on top

for 20nm transistor size, need 5nm silicon (stated in 2011)

bsim: https://bsim.berkeley.edu/ mosfet spice

resistance changes with applied electric field to its surface (applied by the gate - gates current from source to drain)

in 50 years, 1e10 (ten billion) times as many transistors per chip

smaller means lower cost per transistor, less distance so faster (smaller gate delay), less matter so lower power

Modern Semiconductor Devices for Integrated Circuits

there are intel commercials…

ribbon fet, variable width stacks going through the gate (gate all around GAA)

MOS metal oxide (insulator) semiconductor

attracting the few free electrons to the gate with voltage applied

alpha = activity factor is what fraction of clock events that gate switches. clock is 100%, many are 1-10%

perf increased with drive current and min capacitance

switching energy per op is independent of drive current

energy per op reduced by minimizing voltage and cap

cpu clock frequency limited by delay

CMOS complemntary (low stand-by power). combines a pmos and nmos, each turns on in turn to tie output to vdd or ground

low power because no direct path from vdd to ground

negative gate voltage / positive gate voltage

smaller die size can give higher yield

I still don’t quite understand the physical arrangement of gates for a single CMOS (PMOS NMOS pair). they share a gate right? okay N and P are next to each other (or stacked for newer technologies)

NMOS conducts from free electrons, PMOS conducts from holes

next step is 3d stacked cmos where n is stacked over p

wfm - work function metal

analog and sram scale less well with logic in decreasing size. so choose the right size for each and combine as chiplets. interposer is a passive interconnect

podbean was awful. but podcasts are nice

jack kilby integrated circuit nobel lecture

gate-last high-k/metal gate formation : building&removing a temporary gate to place dielectric on fins

dielectric on gate: dielectric layered on top, etched on sides to fill with contact. contacts then get thinned and capped, then contact patch is etched away to expose buried wire

design: combination logic, sequential logic, and timing constraints

80% of effort towards fixing design bugs

technology library and __

foundries / fabless since 80s/90s

x-compact test compression

pat gelsinger ieee cost per test per transistor constant

strained silicon __

there is some repetition in the videos

oxidation: sio2 good insulator 9eV bandgap vs 1.1eV si

gate oxides ~ 10nm to field (separating transistors) 1 um

oxidation rate exponentially dependent on temperature

dopant is thermal diffusion or ion implant

oxidation also used as mask for the dopant

oxidation involves a volume expansion ~2.2x (thickness SiO2 layer / Si layer)

90nm gen: 1.2 nm SiO2 ~ 5 atomic layers amorphous sio2

dry oxidation (with O2) no hydroxyl (H2) so less bridging so denser. wet oxdiation (with H20) does and so can expand more

sio2 growth kinetic (deal grove) model: oxygen has to diffuse through sio2 layer to get to sio2/si boundary and react. uses three fluxes in atomsphere, in oxide, and into si. for thin oxides, growth linear with time. for thick oxides, growth parabolic with time

can use color chart to judge oxide layer thickness by thin-film interference. but the colors repeat at integer multiples

si/sio2 interface: fixed oxide charge (don’t change during operation), interface charges from crystal (do change during operation), mobile oxide charge from contamination (column 1 Na K), oxide trapped charge

characterize si/sio2 interface with a C-V meter (dc sweep with ac), measure current. C effective is series of C oxide and C diffusion through crystal

k is dielectric constant

thin (< 1 nm) sio2 has higher leakage current from tunneling. decrease d is desirable to get higher gate capacitance, so instead we increase k using high-k like hafnium Hf (applied through atomic layer deposition)

ion implantation: control doping position and depth

doping was mainly thermal diffusion, now ion implantation

dopants only electrically active if replace a Si in the crystal structure (substituiontal and not interstitial). which is why ion implantation uses a thermal annealing step to repair crystal damage

thermal diffusion masking is usually sio2 (much lower dopant diffusivity than Si)

diffusion drives dopant from area of high concentration to low

predeposition gets dopant in to an average depth (curve looks like a falling parabola in log concentration)

drive-in: (sometimes after capping with sio2) no dopant in atomsphere, heat to further diffuse the dose deeper and equalize the concentration more

ion source can be impure, use mass turning magnet to filter by mass

raster scan to cover wafer, uses mask (thick(er) sio2, photoresist)

concentration profile can be a gaussian with peak below the surface (at mean depth “projected range” and stddev “straggle”). model is a combination of electronic drag and nuclear collisions

healing an amorphous layer is easier than individualized regions

implant with 6-7 deg tilt to reduce channeling (flying through the gaps in crystal without interaction)

can anneal at varying power density & time (thermal at one end and pulsed laser at the other)

k1 * lam/na k1 includes things like aberration. either decrease wavelength or increase na (related to half angle). k1 >= 0.25

decreasing masking pitch increases the diffraction angle so diffraction orders 1 and -1 move radially outwards to the edge of a lens (for a given size lens). once they move beyond the lens radius, image contrast is lost. but then increase from point to cone illumination so the size of the diffraction spots grows so large that they overlap (like a venn diagram). then the inner portion isn’t being used, so go annular. can eliminate the non-overlapping ring dipole illumination. then use micro mirrors to give light shape control

computational lithography: starting from target shape, iteratively refine light shape and mask pattern to get the best result. does this first with critical subset (I think to converge on as few different light shapes as possible), then fix that (few) light shape and update the rest of the mask (OPC optical proximity correction)

DUV: 135nm, EUV: 13nm

wet chemical etching -> reactive ion etching (gas cold plasma < 1% ionization). also a gas phase etching

HF etches sio2 at rate of 1nm/sec at room temp

rates can be dependent on crystal plane (100 refers to the plane perpinducular to the vector along x)

equipment manufacturers: asml, lam research, tokyo electron limited TEL, applied materials AMAT

reactive ion etching RIE (plasma): electrons stick onto a grounded wafer and then the ions are attracted (like cl) to bond with si, then argon bombards and you get sicl4 flying off. can monitor progress from emission spectra. needs line of sight from top to etch

Strain-induced Self-Rolled-up Membrane wow

thin film deposition: chemical, physical, or liquid vapor deposition

intel 14nm process ~ 2000 steps

epitaxy epi, meaning “above”, and taxis, meaning “in ordered manner”

pvd physical vapor deposition (evaporation or sputtering): for metal heat with current and it evaporates and deposits. ~0.5 nm/s

cvd chemical vapor deposition: goes through chemical reaction; si epitaxy uses sih4 (silene) adsorbs, then 2h2 break off and the si joins the crystal

for si: 100 is the cubic unit structure, 111 is the hexagonal

si substrate 175 um, epitaxial layer 5-25 um

“modern channels use si gn (silicon germanium) alloy”

plasma: mobile electrons can create ions (knocking out another electron from an atom/molecule), dissociate molecules, and excite molecules; wide energy distribution of mixture of products; frequency and power of source (eg 13.56mhz and 360khz (?))

intel 14nm: trigate finfet looks like 2 prong fork with 3 prong fork gate. 8nm fin width and 42nm fin pitch

ald atomic layer deposition: eg al203 aluminum oxide for high k dielectric, top si layer is oxidized with oh, aluminum tri-methyl (remember methane is ch4 methyl is one less hydrogen so alch3(3) aluminum is 3), the oxygen on the surface kicks out a methyl so every si is bonded to alch3(2), purge chamber and add h20 to oxidize the exposed methyls, repeat steps to continue growing al203. is a self-limited surface reaction

Piranha solution/etch: sulfuric acid (H2SO4) and hydrogen peroxide (H2O2)

back end of line interconnects and packaging

al has lower thin film resistivity than cu

cmp chemical mechano polishing: top layer isn’t perfectly flat, etching an uneven surface just propagates that so need planarization. non flat surfae can effect litho since would need light to hit a larger depth of field. cmp usually used after over-applying a material like copper

lab demos: oxidation in gas tube furnace, thermal diffusion/annealing, photoresist in spin coater, photolithography karl suss mjb3, tmah hot wet etch, plasma therm dry etch, pvd sputtering chromium in an argon plasma (dc 250v 20w -> 240w at 30w/min increase I think for metals, ac/rf for dielectrics) pvd sd-400, cvd of amorphous or polysilicon (depending on temperature) in protemp furnace, ald cambridge nanotech fiji f200